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[130.117.225.111]) by mx.google.com with ESMTPS id 5b1f17b1804b1-4a178c82d1esi64833345e9.13.2026.10.06.07.56.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2026 07:56:51 -0700 (PDT) Received-SPF: pass (google.com: domain of khorenko@virtuozzo.com designates 130.117.225.111 as permitted sender) client-ip=130.117.225.111; Authentication-Results: mx.google.com; dkim=pass header.i=@virtuozzo.com header.s=relay header.b=cgsW6uZY; spf=pass (google.com: domain of khorenko@virtuozzo.com designates 130.117.225.111 as permitted sender) smtp.mailfrom=khorenko@virtuozzo.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=virtuozzo.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuozzo.com; s=relay; h=Message-Id:Content-Type:MIME-Version:Subject:Date :From; bh=qEJlbM096ShfP6uQScu2MizNSIShoW7x81TUmuyGOBs=; b=cgsW6uZY1g0YWYJkE5j 1dpB8JI0DtdwBzmiNpX3xr0oEMER7Gw0ZrIFaml2b19VjkskLSP+sI8N7Ml4tR/NsKCBoby/sjnOv EIype7lKCarmTtN3fKkNuTD0Vof6z7B1p5XTfFRoE+SkmP4ZK4uoNLUkMbIdidfWqchvohnxcNf4n qX1y3IIsV4e1nM6xxE5MRWzzO2z/ept/ggEb9MnM6YsDfhvzyD79i5lKHws13e8U5YnZshFG5olz5 Nh8ldImj9HHVhp/3VMvmx2tOrszWAExf9cdUJI83B2kBh18jni4vIz3AHlrRVy966/A3Qj0Wb5Gxe clugNcv9qejom6g==; Received: from ch-demo-asa.virtuozzo.com ([130.117.225.8] helo=f0.sw.ru) by relay.virtuozzo.com with esmtp (Exim 4.96) (envelope-from ) id 1xE6Xq-00DosW-0x; Tue, 06 Oct 2026 16:56:41 +0200 From: Konstantin Khorenko Date: Tue, 06 Oct 2026 16:56:37 +0200 MIME-Version: 1.0 Message-Id: <20261006-b4-prep-khorenko-vstor-148656-cpuid-v1-4-741609f4f03a@virtuozzo.com> References: <20261006-b4-prep-khorenko-vstor-148656-cpuid-v1-0-741609f4f03a@virtuozzo.com> In-Reply-To: <20261006-b4-prep-khorenko-vstor-148656-cpuid-v1-0-741609f4f03a@virtuozzo.com> To: Pavel Tikhomirov , Vasileios Almpanis X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2740; i=khorenko@virtuozzo.com; h=from:subject:message-id; bh=6m/g5pNf/ipAkqDG11BqXp81XqDDJtv6EHkd+2i5fHM=; b=owEBbQKS/ZANAwAKAVGWCkf5YVwqAcsmYgBqxQwx9xVAOTRDfdCCS1c7wCOWIedQDAv56Q9Ap ZmruaPLWZaJAjMEAAEKAB0WIQRWD23IPcXT0GO9CCxRlgpH+WFcKgUCasUMMQAKCRBRlgpH+WFc KspSEAC2Z/a1y0cJHwPKFM/EjWjH53bN9KRfNQWTD0COqnjFO87P353Oa9HbQK1ytUPTB6sDZT5 EfRmXixhornLR4KBlVzP88BMFFXKsv/LBWlUFT6geYBsAPgsoW+8GaY3edBdIzwZoNZYjfdgavQ usbnmRod2njbot6zChliLr46s6UIB2rwWr6oAxLta3CdqcSartEAorYi2Khn15ak80xks+vaLZX sbNwp7qT+u9AACteIBtxrQ+Nd1rfz9kwDowMn1nO9Yk/K0Y5UBR3PcCMHmRB6wRS4WftpmjLh15 nxMgJwx4s2fqpLyYGO9TBoG28CfshbNxEi7ZVdwORhh/DofLkoVTuIi72fNzA7mgKZQj/IbHDJ4 mWFC7belWjxTGXBIIKgtC0RCFpKspNo/ocU9ob5aUjPc93EJfr7w4ykyJfF8jBXctnHT3CotCQ8 BDK9rdtEqDQBcbu1HcCJsIQomnCUBTEBnP9uUVal8R/cE2gS5cWHcTm0jT938l+vYW7aACqy7l0 6y7JmTOwdbrrWoZrEbqy7aTP5KynWR/e4P8tfzAaNGRjY7wfxq5VzuvdgMwKU1lhpj2Idv2Fvfw fG73UBqg6mYPZZr48UR+A5AjaDQllJX9W4Droww/Cj1dJOWzIml3UBsW4vvW5e5U1AqXw/1o3VT pfUc/vP100rN/Hg== X-Developer-Key: i=khorenko@virtuozzo.com; a=openpgp; fpr=560F6DC83DC5D3D063BD082C51960A47F9615C2A X-OZ-Fwd: true Cc: devel@openvz.org Subject: [Devel] [PATCH hci-8.1 4/5] x86/traps: decode the faulting CPUID with the instruction decoder X-BeenThere: devel@openvz.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: OpenVZ development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: devel-bounces@openvz.org Errors-To: devel-bounces@openvz.org check_cpuid_fault() reads two bytes at the faulting ip and emulates only when they are 0f a2, the bare CPUID encoding. CPUID has no operands, so the CPU accepts and ignores every legacy and REX prefix in front of it. All of these are valid CPUID and raise the same #GP(0) when CPUID faulting is on: 0f a2 cpuid 66 0f a2 data16 cpuid (operand-size override) f3 0f a2 repz cpuid 2e 0f a2 cs cpuid (segment override) 48 0f a2 rex.W cpuid Only the first one is recognised. For the others the handler reads the prefix byte instead of the opcode, declines, and the task is killed with SIGSEGV although the instruction is legal and the host would have executed it. Such encodings could come from hand-written and generated assembly, from binary translators and JITs that emit prefixes for alignment or as padding, and from any binary that disassembles as "data16 cpuid" rather than "cpuid". Fetch and decode the instruction with insn_fetch_from_user() and insn_decode_from_regs(), as fixup_umip_exception() does, match the opcode bytes and advance ip by the decoded length. The decoder derives the linear ip from the code segment itself, so convert_ip_to_linear() is not needed any more. Fixes: 1033fe455434 ("arch/x86: introduce cpuid override") https://virtuozzo.atlassian.net/browse/VSTOR-148843 Feature: x86: cpu pools (cpuid override) Signed-off-by: Konstantin Khorenko --- arch/x86/kernel/traps.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 8074387bf4f43..fa12da67adbf0 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -633,8 +633,9 @@ static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, static int check_cpuid_fault(struct pt_regs *regs, long error_code) { - unsigned long addr; - unsigned short opcode; + unsigned char buf[MAX_INSN_SIZE]; + struct insn insn; + int nr_copied; if (error_code != 0) return 0; @@ -642,16 +643,19 @@ static int check_cpuid_fault(struct pt_regs *regs, long error_code) if (test_thread_flag(TIF_NOCPUID)) return 0; - addr = convert_ip_to_linear(current, regs); - if (get_user(opcode, (unsigned short __user *)addr)) + nr_copied = insn_fetch_from_user(regs, buf); + if (nr_copied <= 0) + return 0; + + if (!insn_decode_from_regs(&insn, regs, buf, nr_copied)) return 0; - if (opcode != 0xa20f) + if (insn.opcode.bytes[0] != 0x0f || insn.opcode.bytes[1] != 0xa2) return 0; do_cpuid_fault(regs); - regs->ip += 2; + regs->ip += insn.length; return 1; } -- 2.43.0 _______________________________________________ Devel mailing list Devel@openvz.org https://lists.openvz.org/mailman/listinfo/devel